The FORBIDDEN Motherboard!! Hacking More Lanes into AM5: LR-Link Broadcom PCIe Expansion

TL;DR

Using an LR-Link Broadcom PCIe 5 bridge card, you can expand AM5's limited PCIe lanes to run four GPUs simultaneously with inter-GPU communication bypassing the CPU.

Key Points

• 1.AM5 has a fundamental PCIe lane shortage for multi-GPU workloads. Desktop AM5 CPUs offer roughly 20–24 PCIe lanes total, meaning two GPUs typically share 8 lanes each rather than getting the full 16, limiting bandwidth for AI training and inferencing.
• 2.The LR-Link Broadcom PCIe 5 bridge card takes 16 Gen 5 lanes in and outputs 32 Gen 5 lanes out. Originally designed for NVMe expansion (up to eight 4-lane U.2 drives), its Broadcom chipset is reprogrammable, allowing it to be reconfigured for GPU slots or mixed PCIe devices.
• 3.Reprogramming the Broadcom bridge enables four R9700 GPUs (128GB VRAM) on a single AM5 system. GPUs communicate peer-to-peer through the bridge at full PCIe Gen 5 x16 bandwidth without routing data through the CPU, mirroring what Nvidia's ConnectX-9 does in high-end AI servers.
• 4.Real-world benchmarks show 10–20% performance gains over a standard dual-GPU setup. Two R9700s running Qwen 3.6 through the LR-Link bridge hit ~125 tokens/second vs. 107 tokens/second without it; fine-tuning tasks see up to 15% improvement, and RTX 6000-class cards can see up to 20% gains.
• 5.The card costs over $1,000 and requires manual PCIe bridge reprogramming — not plug-and-play. For standard bifurcation use cases, LR-Link's passive retimer/redriver cards are cheaper and simpler; the Broadcom bridge is justified mainly for PCIe AER error fixing, compatibility issues, or maximizing multi-GPU bandwidth.
• 6.PCIe lanes are fungible and can be spent on GPUs, NVMe, U.2, networking, or expansion via MCIO cables. LR-Link's MCIO connectors support breakout boards with multiple x8 or x16 slots, IcyDock M.2 carriers, and U.2 adapters, letting builders route bandwidth wherever the workload demands.
• 7.The presenter's AM6 fantasy spec calls for 30–32 PCIe Gen 6 lanes from the CPU with a two-chipset layout. The wishlist includes 16 lanes for GPUs, 8 lanes to the chipset over Gen 6, 4 lanes direct to M.2, and 2 Gen 6 lanes for rear IO — pointing to a Chinese AM4 board that already achieved 32 lanes as proof of concept.